Verilog USB 1.1

As part of the ECE 337 Final Project, I worked alongside Nahom Tadesse and Peter Kim to make a USB 1.1 Transceiver.

I was responsible for the AHB-Lite Bus Interface, while the other group tasks included USB Transmitter, USB Receiver and a centralized FIFO data buffer. Work included RTL Diagramming, source file development in SystemVerilog, followed by testbenching/waveforms using QuestaSim.